1. Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of local oxidation using modified junction depth around the bird's beak to reduce junction leakage in the fabrication of integrated circuits.
2. Description of the Prior Art
Local oxidation of silicon is the conventional lateral isolation scheme. The conventional local oxidation process (LOCOS) is described in VLSI Technology, International Edition, by S. M. Sze, McGraw-Hill Book Company, N.Y., N.Y., c. 1988 by McGraw-Hill Book Co., pp. 473-474. Referring to FIG. 1, a layer of silicon nitride 3 is deposited over a pad oxide 2 overlying a silicon substrate 1. The pad oxide is a thin thermal oxide which allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxide formation. The nitride and oxide layers are etched to leave openings 4 exposing portions of the silicon substrate where the local oxidation will take place. A boron channel-stop layer 5 is ion implanted into the isolation regions. Referring now to FIG. 2, the field oxide 6 is grown within the openings.
There are many disadvantages to the conventional LOCOS method. Bird's beak encroachment 7 is caused by the lateral oxidation of silicon along the pad oxide under the nitride layer. Other disadvantages include the white ribbon effect caused by the diffusion of nitrogen-like material from the compressive-stressed nitride layer edge into the neighboring underlying tensile-stressed pad oxide layer, width narrowing, non-recessed surface, and tremendous stress generated during high-temperature oxidation of silicon. Many crystalline defects 8 including dislocations and stacking faults are generated by the relaxation of these tremendous stresses around the bird's beak. Because p+/n or n+/p junctions, shown as 9 in FIG. 3, occur in the area of the bird's beak 7, these crystalline defects 8 intersect the junctions resulting in leakage paths. Low power devices, for example, 1M static random access memory (SRAM), 4M SRAM, etc., require a very tiny leakage current of about 0.degree. 5 pA, within the standby current specification of about 0.5 .mu.A, to prevent data loss. Using conventional LOCOS processes, the junction leakage through stress-induced defects is too large, about 1 pA per cell, to be acceptable during device operation.
FIG. 4 illustrates the misalignment of a contact. Gate electrode 61 is covered by insulating layer 62. A contact opening has been made through the insulating layer 62 to contact the source/drain region 9. However, the contact opening is misaligned. The misalignment of the contact pattern exposes some of the FOX 6 region. This region 6 is etched away to expose the underlying substrate during the contact etching process. When the contact is filled with metal 64, the inevitable short from metal to substrate will cause the function to fail.
To avoid the shorting problem due to misalignment, a plug or contact implant is made, as illustrated in FIG. 5. The plug or contact implant 63 is performed after the contact etching to ensure that the metal will contact to a heavily doped source/drain area even if there is a misalignment during contact pattern definition. Typically the dosage of the plug or contact implantation is similar to the previous source/drain implantation and a post thermal treatment, such as higher than 800.degree. C. for about 30 minutes, is needed for dopant activation. The plug or contact implantation has been a popular process in the fabrication of submicron Very Large Scale Integrated (VLSI) circuits. However, even with the presence of the plug or contact implantation, LOCOS induced defects cause unacceptable junction leakage.
U.S. Pat. No. 4,986,879 to Lee teaches a method of local oxidation using a thick pad oxide layer and a thin silicon nitride sidewall to release stress. U.S. Pat. No. 4,981,813 to Bryant et al teaches a method using silicon nitride sidewalls and recessed silicon to fabricate a narrower width field oxide region with a reduced bird's beak. U.S. Pat. No. 5,139,964 to Onishi et al uses a silicon nitride sidewall and a substrate recessed under the sidewall to achieve local oxidation with reduced stress and a higher breakdown voltage. However, more or less LOCOS induced stress is still there to generate crystalline defects resulting in unacceptable junction leakage.